Does the port address correspond to the logical address

The internal ports of the HD64180 Helmut Bernhardt All additional services made available in the HD64180 compared to the Z80 must be programmed via port addresses. An I / O address range of 3FH ports is required for these internal ports of the CPU. As in principle with the Z80, an I / O address space of 64K ports can be differentiated with the HD64180. With the Z80, only the commands IN A, (C) and OUT (C), A are useful for this. With these commands, the contents of registers C (AO-A7) and B (A8-A15) are placed on the bus as addresses. With the normal IN and OUT commands with the output of an 8-bit port address in the command operand, the content of the Accu is placed on A8-A15 of the address bus. These commands cannot be used in systems whose I / O address decoding is based on 16-bit addresses. The internal ports of the HD64180 are on the zero page (A8-A15 are low) of the 64K address space. To read and write these internal ports, the HD64180 has special commands that automatically output A8-A15 low when the internal ports are accessed. Traditionally, however, all I / O-mapped peripheral devices for Z80 systems only decode A0-A7 and thus limit the I / O address space to 256 ports. When the internal ports are accessed, these modules also feel that they are being addressed if their 8-bit address matches the zero page address of the internal port being addressed. When reading an internal port, the data drivers of the HD64180 chip are therefore closed to the environment, so that no collisions between internal and external data are possible. When writing, however, the data intended for the internal ports also reach the outside and are also received by an external port at the same address. Peripheral devices playing crazy would be the result, if an additional fuse were not built into the HD6418O. The contiguous address range of 3FH zero-page ports for the registers of the HD64180 starts at 00H by default. By changing bits 7 and 6 of the IRC register (3FH), the 3FH ports can be shifted within the zero page. D7 D6 Address area of ​​the internal ports -------------------------------------------- ------- 0 0 00 - 3F (after RESET) 0 1 40 - 7F 1 0 80 - BF 1 1 C0 - FF ------------------- -------------------------------- The port address information used below assumes that D6 and D7 from ICR are both are low and the internal ports are at 00-3F in the zero page. The relative addresses and functions can be seen in the table from the Prof-180 manual. With this table alone you are far from being able to program the internal ports in a meaningful way. Perhaps the following remarks will help: First of all, the information on the IRC register, 'I / O Control Register', Port 3H) should be completed. D5 (IOSTP) = 0 enables normal operation of the H64180 internal peripheral ports (setting after RESET). If ISTP is set to 1, the functions of ASC1, CSi / 0 and PRT (serial interfaces and reload timer are disabled. So that an HD64180 ticking at 9.26 MHz clock rate can also run with slow peripherals, there is not only the WAiT -Pin, via which the periphery can ask the CPU for patience; the CPU (and also the internal DMA channels) can also insert WAIT cycles independently, with between memory-mapped I / O and I / O-mapped accesses Different numbers of WAITs can be set with the upper nibble of port 32H (DCNTL); D7 D6 Number of WAITs with memory mapped addressing ---------------------- ----------------------------- 0 0 0 0 1 1 1 0 2 1 1 3 (after RESET) ----- ---------------------------------------------- Number of WAITs for - -------------------------------------------------- D5 D4 I / O accesses / INT0-Acknowledge 0 0 1 2 0 1 2 4 1 0 3 5 1 i 4 6 --------------------------------------------- ------ When accessing the internal ports, no WAITs are inserted regardless of D5 and D4. Only for the data registers of ASCI, CSI / O and PRT, depending on the status, up to 4 WAITs are inserted for synchronization with the CPU. Bits 0-3 of DCNTL are used to control DMA operation and are dealt with there. RCR, Refresh Control Register, Port 36H Compared to the hidden refresh of the Z80 during each M1 cycle, the HD64180 outputs an 8-bit refresh address after a certain number of clock cycles. The 8-bit address means that 256K-bit and 1M-bit memory chips can be used without additional refresh logic. A refresh takes place asynchronously to the CPU work after a number of clock cycles set via RCR D0 and D1: D1 D0 number of clocks between two refresh cycles --------------------- ------------------------------ 0 0 10 0 1 20 1 0 40 1 1 80 -------- ------------------------------------------- With D7 = 0 at RCR the refresh controller switched off (refreshing can be omitted for static RAMs. D7 = 1 (after RESET) activates the refresh controller. #################### With D0 the refresh timing can be adapted to the possibilities of the memory: D0 = 0: Refresh is 2 clock cycles long D0 = 1: Refresh is 3 clock cycles long (preset after RESET) D2-D5 in the RCR register have no function. ICT, Interrupt / trap register, port 34H D7 (trap) is always set to 1 by the CPU when it has encountered an illegal command (eg undefined Z80 commands). D7 can be set to 0 again with an OUT0 command (no but on 1). After RESET, D7 = 0. An illegal op-code triggers the trap interrupt, which has the highest priority for the HD64180. The service routine can then recognize from the status of D6 (UFO) whether the error occurred in the 2nd or 3rd byte of the op code. D6 allows the correction of the program counter saved on the stack after the trap. If D6 = 0, the rescued PC points to the second byte of the command recognized as incorrect. If D6 = 1, the PC points to the 3rd byte of the wrong command. D6 can only be read. D0, D1 and D2 can be used to mask the external interrupt / INT0, / INT1 and / INT2. If the corresponding bit is set to 0, the interrupt is blocked: when set to 1, the corresponding interrupt is enabled. After a RESET, only / INT0 is enabled (D0 = 1) and / INT1 and / INT2 are blocked (D1, D2 = 0). IL, Interrupt Vector Low Register, Port 33H The external interrupts / INT0 in mode 2 as well as / INT1 and / INT2 and all internal interrupts are served by service routines whose start addresses are stored in a table. The technology is that of the IN2 in the Z80. The upper 8 bits (A8-A15) of the address of the vector table are stored in the I register of the CPU. The lower 8 bits of the address (pointer in the vector table) are supplied by the interrupt-triggering peripheral device in the interrupt acknowledge- ment via the data bus. The CPU ignores D0 of this in order to generate an even address and uses the two halves to create a pointer in the vector table. The address stored there in the table is the start address of the service routine. With the HD64180 only the / INT0, which corresponds to the / INT of the Z80 in mode 2, needs an externally supplied address part (A0-A7 via D0-D7) of the data bus in order to find the address of the service routine in the vector table. This means that several INT sources can be connected alternately via just one interrupt input on the CPU. The addresses of the other interrupt sources of the HD64180 are fixed (with a certain degree of freedom). The first two bytes of the table (address with A0-A7 = 0) represent the address with the service routine for / INT1. The next two bytes supply the vector for / INT2. The order of the vectors is determined by the interrupt sources; however, the relative position of the group of vectors (32 bytes) within the 256-byte table can be shifted in 32-byte steps. The location of this address group in the table is specified by D7-D5 of the IL register (after RESET these are low and the group is at the beginning of the vector table). if D7-D5 are all low, the vectors for / INT1, / INT2 and the internal interrupts are in the table from address XX00H; if D7-D5 have the bit pattern 001, these vectors are in the table from XX20H; etc. Bits 0-4 are generated by the internal interrupt source itself and specify the relative address within the 32-byte group in the table. Table 2.7.2 of the 64180 manual (which is reproduced here without the kind permission of Hitachi) specifies the order of the entries for the interrupt sources and the associated priority hierarchy. Table 2.7.2 Interrupt Source and Lower Vector ----------------------------------------- --------- Interrupt- Priority IL Fixed Code -Source b7 b6 b5 b4 b3 b2 b1 b0 / INT1 highest. . . 0 0 0 0 0 / INT2. . . 0 0 0 1 0 PRT channel 0. . . 0 0 1 0 0 PRT channel 1. . . 0 0 1 1 0 DMA channel 0. . . 0 1 0 0 0 DMA channel 1. . . 0 1 0 1 0 CSI / 0. . . 0 1 1 0 0 ASCI channel 0. . . 0 1 1 1 0 ASCI channel 1 lowest. . . 1 0 0 0 0 --------------------------------------------- ----- In addition to the masked interrupts, there is also the trap mentioned above, which results in a branch to the logical address 0000H. If this logical address is identical to the physical address 0000H (banking), this corresponds to the / RESET vector. By checking D7 in port 32H (ICT) it can be seen whether there is a trap or a RESET. As with the Z80, a / NMI causes a CALL 00066H, whereby the logical address within the set bank and not necessarily the absolute address 00066H is also relevant here. The / INT0, like the / INT of the Z80, knows modes 0 and 1, Mode 0: With Acknowledge, a 1-byte command is read from the data bus and executed (RST XX) This byte must supply the interrupt source. Mode 1: In the event of an interrupt on the / INT0 pin, an RST 38H occurs. The address 0038H is in the bank set by MMU (logical address). Further controls of the internal interrupts are shown in the description of the respective function groups. But only in the next info. Table 2.5.33H INT / TRAP Register 34H (Reserved) 35H Refresh Refresh Control Register RCR 36H (Reserved) 37H MMU MMU Common Base Register CBR 38H MMU Bank Base Register BBR 39H MMU Common / Bank Area Register CBAR 3AH I / O (Reserved) 38H-3EH I / O Control Register ICR 3FH